Microchip Technology /ATSAMV70J20B /TWIHS0 /IER

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Interpret as IER

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TXCOMP)TXCOMP 0 (RXRDY)RXRDY 0 (TXRDY)TXRDY 0 (SVACC)SVACC 0 (GACC)GACC 0 (OVRE)OVRE 0 (UNRE)UNRE 0 (NACK)NACK 0 (ARBLST)ARBLST 0 (SCL_WS)SCL_WS 0 (EOSACC)EOSACC 0 (MCACK)MCACK 0 (TOUT)TOUT 0 (PECERR)PECERR 0 (SMBDAM)SMBDAM 0 (SMBHHM)SMBHHM

Description

Interrupt Enable Register

Fields

TXCOMP

Transmission Completed Interrupt Enable

RXRDY

Receive Holding Register Ready Interrupt Enable

TXRDY

Transmit Holding Register Ready Interrupt Enable

SVACC

Slave Access Interrupt Enable

GACC

General Call Access Interrupt Enable

OVRE

Overrun Error Interrupt Enable

UNRE

Underrun Error Interrupt Enable

NACK

Not Acknowledge Interrupt Enable

ARBLST

Arbitration Lost Interrupt Enable

SCL_WS

Clock Wait State Interrupt Enable

EOSACC

End Of Slave Access Interrupt Enable

MCACK

Master Code Acknowledge Interrupt Enable

TOUT

Timeout Error Interrupt Enable

PECERR

PEC Error Interrupt Enable

SMBDAM

SMBus Default Address Match Interrupt Enable

SMBHHM

SMBus Host Header Address Match Interrupt Enable

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